SRAMs may be arranged in a domino-logic structure with a local bit line coupled to a number of SRAM cells and a global bit line that may be discharged when the local bit line is discharged. SRAM cells are connected in parallel to write/precharge logic through the local bit line. The local bit line in a domino SRAM is precharged high by the write/precharge logic and may be discharged to ground by a selected cell during a read operation. The local bit line is coupled to a transistor which may discharge the global bit line. In order for the SRAM circuit to function, the global bit line must be precharged.
FIG. 1 is a schematic representation of a portion of a prior art SRAM circuit 100 having local evaluation logic 106, a global bit line (GBL) 102, and global bit line precharge logic 107. The local evaluation logic 106 contains write/precharge logic 101 and global bit line discharge logic 108. One or more SRAM cells 105 are connected to the write/precharge logic 101 and the global bit line discharge logic 108 via a local bit line (LBL) 104, and are accessed by a word line (WL) 109. For a read operation, LBL 104 is precharged by the write/precharge circuit 101 and may be discharged by a selected SRAM cell 105. GBL 102 is precharged by the global bit line precharge logic 107 and discharged by the global bit line discharge logic 108.
As an illustration, to read a “zero” from a cell 105, the selected SRAM cell 105 may pull down the precharged LBL 104. The “zero” value on LBL 104 is inverted to a “one” by either an inverter 1I1 for configurations where only one group of cells is connected to local evaluation logic 106 or a NAND gate for configurations where two groups of cells are connected to local evaluation logic 106, and turns on a transistor 1N1, which pulls down the precharged GBL 102. GBL 102 is sampled and subsequently precharged for a next operation by a global bit line precharge line (GBL_PCH) 103 and an associated transistor 1P1.